View CXA1866Q_138539.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA1866Q
6-bit 140MSPS Flash A/D Converter For the availability of this product, please contact the sales office.
Description The CXA1866Q is a 6-bit ultra-high-speed flash A/D converter IC capable of digitizing analog signals at the maximum rate of 140MSPS. The digital input level is compatible with ECL 100K/10KH/10K. Features * Ultra-high-speed operation with maximum conversion rate of 140MSPS * Low input capacitance: 7pF * Wide analog input bandwidth: 210MHz * Low power consumption: 325mW * Low error rate * Excellent temperature characteristics * 1 : 2 demultiplexed output (TTL level)
VRBS
48 pin QFP (Plastic)
Structure Bipolar silicon monolithic IC Applications * Magnetic recording (PRML) * Communications (QPSK, QAM) * Liquid crystal display
VRTS
22
15
19
VRB 16
VIN
Block Diagram
Reference Resistance Chain
21
VRT
COMPARATOR
6bit Latch 41 DVEE 6 INV 27 CLatchA CD NCCLK 25 46 DGND1 23 AVEE
CCLK 26
20 AGND
45 DGND2 42 DGND3 CLatchB 6 DCLK 11 CD NDCLK 12 TTLOUT 47 6 48 DVCC2 DVCC1
7
6
5
4
3
2
35 34 33 32 31 30
CD; Clock Driver
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
P2D5 (MSB)
-1-
P1D5 (MSB)
P2D0 (LSB)
P1D0 (LSB)
P2D4
P2D3
P2D2
P2D1
P1D4
P1D3
P1D2
P1D1
E93Z35B77
CXA1866Q
Absolute Maximum Ratings (Ta = 25C) * Supply voltage AVEE, DVEE DVCC1 * Analog input voltage VIN * Reference input voltage VRT, VRB I VRT - VRB I * Digital input voltage DIN2 I CCLK - NCCLK I, I DCLK - NDCLK I * Digital output current ID0 to ID6 * Storage temperature Tstg * Ambient operating temperature Ta * Allowable power dissipation PD Recommended Operating Conditions * Supply voltage AVEE, DVEE AVEE - DVEE AGND - DGND3 DVCC1 * Reference input voltage * Analog input voltage * Digital input voltage * * * * * * CCLK, NCCLK frequency DCLK, NDCLK frequency CCLK, NCCLK duty DCLK, NDCLK duty CCLK-DCLK time difference4 Operating temperature VRT VRB VIN DIN (H) DIN (L) Fcclk Fdclk Dcclk Ddclk tdcd Ta Min. -5.5 -0.05 -0.05 4.75 -0.1 -2.2 VRB -1.1
-7.0 to +0.5 0.5 to +7.0 -2.7 to +0.5 -2.7 to +0.5 2.5 -4.0 to +0.5 2.5 -30 to +30 -65 to +150 -20 to +75 750 Typ. -5.2 0 0 5.0 0 -2.0 Max. -4.75 0.05 0.05 5.25 0.1 -0.8 VRT -1.5 140 70 60 60 TPWH + 1 +75
V V V V V V V mA C C mW
V V V V V V V V MHz MHz % % ns C
40 40 -TPWL + 2 -20
50 50 0
1 DVCC = DVCC1, DVCC2 2 DIN = CCLK, NCCLK, DCLK, NDCLK, INV
P1D5 (MSB)
3 DGND = DGND1, DGND2, DGND3 4 Refer to the Timing Chart 1 for TPWL, TPWH.
P1D0 (LSB)
DGND3
DGND3
DVCC2
P1D4
P1D3
36 35 34 33 32 31 30 29 28 27 26 25
DVCC2 37 DVCC1 38 DGND1 39 DGND2 40 DVEE 41 DGND3 42 DVCC2 43 DVEE 44 DGND2 45 DGND1 46 DVCC1 47 DVCC2 48 CXA1866Q (Top View)
INV
CCLK
P1D2
P1D1
NCCLK
Pin Configuration. Pins without names are NC pins (not connected).
24 23 22 21 20 19 18 17 16 15 14 13 AGND VRB VRBS AVEE AVEE VRTS VRT AGND VIN
1
2
3
4
5
6
7
8
9 10 11 12
P2D5 (MSB)
DGND3
P2D0 (LSB)
-2-
DGND3
NDCLK
P2D4
DVCC2
DCLK
P2D1
P2D2
P2D3
CXA1866Q
Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O
Standard voltage level
VRT
Equivalent circuit
Description Top reference voltage input (= 0V). This is the top reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the plus side of the input analog signal amplitude. VRT sense output. This is the voltage sense pin for VRT. Bottom reference voltage input (= -2V). This is the bottom reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the minus side of the input analog signal amplitude. VRB sense output. This is the voltage sense pin for VRB.
AGND
21
VRT
I
0V
VRTS
Comparator 1
22
VRTS
O
0V
Comparator 2
Comparator 31
Comparator 32
16
VRB
I
-2V
Comparator 63 VRBS
15
VRBS
O
-2V
VRB
19
VIN
I
VRTS to VRBS
VIN
Analog input. The input range is 2Vp-p.
AVEE
26
CCLK
I
ECL
CCLK clock input. This is the conversion clock, and is an ECL level input. CCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only CCLK input can be used for operation with the NCCLK input left open,but complementary input is recommended to attain fast and stable operation. DCLK clock input. This is the 1:2 DMPX latch clock; input a clock of 1/2 frequency of CCLK. Data are output from DMPX port 1 and port 2 synchronously with the rising edge of this signal. This is an ECL level input. DCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only DCLK input can be used for operation with the NDCLK input left open, but complementary input is recommended to attain fast and stable operation. -3-
DGND1
25
NCCLK
I
ECL
r CCLK (DCLK) NCCLK (NDCLK) r 500 r r
500
11
DCLK
I
ECL
r DVEE
r 1.3V
12
NDCLK
I
ECL
CXA1866Q
Pin No.
Symbol
I/O
Standard voltage level
DGND1
Equivalent circuit
Description
r r 1.3V
27
INV
I
ECL
INV
500
r
r DVEE
1.3V
Digital output polarity inversion input. This is an ECL level input. This input inverts the polarity of the digital outputs P1D0 to P1D5, and P2D0 to P2D5. (Refer to the Output Code Table.) When left open, this signal is maintained at the low level.
30 31 32 33 34 35 2 3 4 5 6 7
P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 -- -- -- -- -- +5.0V +5.0V 0V 0V 0V +5V power supply for TTL level internal circuit. +5V power supply for TTL level output buffers (P1D0 to P2D5). Ground for DVEE digital circuit. Ground for DVcc1 digital circuit. Ground for DVcc2 digital circuit. Ground for AVEE analog circuit . Used as the ground for the comparator input buffers, latches, etc. Separated from DGND. -5.2V power supply for digital circuit. Connected internally with AVEE. (Resistance is 4 to 6.) -5.2V power supply for analog circuit. Connected internally with DVEE. (Resistance is 4 to 6.)
DGND2 DGND3 DVCC1 DVCC2
These pins are for the 6 bits of digital output data for DMPX port 1. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs.
O
TTL
100K
P1D0 to D5 P2D0 to D5
These pins are for the 6 bits of digital output data for DMPX port 2. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs.
38, 47 DVCC1
9, 28, 37, DVCC2 43, 48
39, 46 DGND1
40, 45 DGND2
1, 8, 29, DGND3 36, 42
17, 20 AGND
--
0V
41, 44 DVEE
--
-5.2V
14, 23 AVEE
--
-5.2V
-4-
CXA1866Q
Electrical Characteristics Item Resolution DC characteristics Integral linearity error Differential linearity error No missing code Analog input Analog input capacitance Analog input resistance Input bias current Reference input Reference resistance Reference resistance current Offset voltage VRT VRB Digital input Logic high level Logic low level Logic high current Logic low current Input capacitance Switching characteristics Maximum conversion frequency Aperture jitter Sampling delay Digital output Logic high level Logic low level Output delay Output rising time Output falling time Dynamic characteristics Analog amplitude input bandwidth S/N ratio Symbol n EIL EDL
(Ta = 25C, AVEE = DVEE = -5.2V, DVCC = 5V, VRT = 0V, VRB = -2V) Conditions Min. Typ. 6 Fc = 140MHz Fc = 140MHz Guaranteed CIN RIN IIN RREF Iref EOT EOB VIH VIL IIH IIL -1.13 VIH = -0.8V VIL = -1.6V 0 -50 3.5 FC Taj Tds VOH VOL tdo tr tf Finb IOUT = -2mA IOUT = 1mA ZL = 25pF ZL = 25pF, 0.5V to 2.4V ZL = 25pF, 0.5V to 2.4V 2.7 2.0 1.2 1.2 210 36 34 32 10-9 20 -40 325 32 0.5 8.0 Error rate1E-9 TPS1 140 5.0 1.0 -1.50 50 50 VIN = -1V + 0.07Vrms, DC VIN 70MHz -2V VIN 0V -2V VIN 0V 7 200 110 225 9 25 25 pF k A mA mV mV V V A A pF MSPS ps ns V V ns ns ns MHz dB dB dB TPS1 mA mA mW 0.2 0.2 Max. Unit bits LSB LSB
Error rate Power supply Supply current Power consumption 1 TPS: Times Per Sample
VIN = 2Vp-p, p-p value = 3dB down input frequency SNR1 Fc = 140MHz, Fin = 1MHz SNR2 Fc = 140MHz, Fin = 35MHz SNR3 Fc = 140MHz, Fin = 70MHz Fc = 140MHz, error > 4LSB ICC IEE Pd DVCC = +5V AVEE = DVEE = -5.2V
-60
-5-
CXA1866Q
Output Code Table VIN 0V STEP 0 1 31 32 INV = 0 D5 INV = 1 D0
D0 D5
-1V
-2V
63
000000 000001 : 011111 100000 : 111110 111111
111111 111110 : 100000 011111 : 000001 000000
INV = 0: low level; INV = 1: high level
Timing Chart 1
tds VIN N-1 N N+1 N+2 N+3 N+4 tr tf -1.1V CCLK -1.5V -1.3V
Dcclk
TPW H
TPW L
NCCLK Ddclk
-1.3V
tdcd
tf
tr -1.1V
DCLK -1.5V
-1.3V
NDCLK tdo tdo 2.0V P1D0-5 1.0V N-4 N-2 N
-1.3V
2.0V P2D0-5 1.0V N-3 N-1 N+1
-6-
CXA1866Q
Timing Chart 2
6 VIN COMPARATOR 6bit Latch CLatchA 6 CLatchB 6
CCLK 6 TTLout P1D0 to D5
DCLK 6 TTLout 6 P2D0 to D5
N-1
N
N+1
N+2
N+3
N+4
N+5
VIN
CCLK
COMPARATOR (master)
N-1
N
N+1
N+2
N+3
N+4
N+5
COMPARATOR (slave)
N-1
N
N+1
N+2
N+3
N+4
N+5
6bit Latch
N-2
N-1
N
N+1
N+2
N+3
N+4
CLatchA
N-3
N-2
N-1
N
N+1
N+2
N+3
CLatchB
N-4
N-3
N-2
N-1
N
N+1
N+2
DCLK
TTLout (P2D0 to D5)
N-3
N-1
N+1
TTLout (P1D0 to D5)
N-4
N-2
N
-7-
CXA1866Q
Electrical Characteristics Measurement Circuit Maximum conversion rate measurement circuit
6 VIN Signal Source fCLK DUT CXA1866Q 6 Latch A B -1kHz 4 2Vp-p Sin Wave CCLK DCLK + Latch Comparator A>B Pulse Counter
Data 4 Signal Source fCLK
Amp
1/2
Integral linearity error measurement circuit Differential linearity error measurement circuit
+V
S1 S1: ON when A < B S2: ON when A > B S2
-V
(P1D0 to D5)
6 VIN DUT CXA1866Q SW
6
(P2D0 to D5)
AB Comparator A6 B6 to to A1 B1 A0 B0
6 Buffer
"0" CCLK DCLK
"1" 000000 to 111110
6 DVM Controller
-8-
CXA1866Q
Current consumption measurement circuit Analog input bias measurement circuit
36 35 34 33 32
31 30 29 28 27 26 25
DGND3
DGND3
37 DVCC2 38 DVCC1 39 DGND1 40 DGND2 41 DVEE 42 DGND3 43 DVCC2 44 DVEE 45 DGND2 46 DGND1 47 DVCC1 CXA1866Q
NCCLK
P1D3
DVCC2
P1D4
P1D0
INV
CCLK
P1D5
P1D2
P1D1
24 AVEE 23 VRTS 22 VRT 21 AGND 20 VIN 19 18 AGND 17 VRB 16 VRBS 15 AVEE 14 -2.0V IIN
A
-1.0V
DGND3
DGND3
48 DVCC2
13
DVCC2
P2D0
P2D3
1
2
3
4
5
6
P2D4
7
8
9
10 11 12
ICC
DCLK
P2D2
P2D1
P2D5
NDCLK
IEE
A
+5.0V
A
-5.2V
Sampling delay measurement circuit Aperture jitter measurement circuit
VIN Signal Source1 : variable CXA1866Q
6 Logic Analizer 6 SW
Freq Lock
CCLK
DCLK
1024 samples
Signal Source2 ECL Buffer
-9-
CXA1866Q
Electrical Characteristics
Current comsumption vs. Ambient temperature
ICC IEE -30 (VEE = -5.2V, VCC = +5.0V) 25.0
IEE - Current consumption [mA]
ICC - Current consumption [mA]
-35
22.5
-40
20.0
-45
17.5
-50 -25
15.0 0 25 Ambient temperature [C] 50 75
VOH vs. Ambient temperature
3.6 (VEE = -5.2V, VCC = 5.0V, IOUT = -2mA)
VOH - Digital output level [V]
3.5
3.4
3.3
3.2
3.1 -25
0
25 Ambient temperature [C]
50
75
VOL vs. Ambient temperature
(VEE = -5.2V, VCC = 5.0V, IOUT = 1mA) 0.40
VOL - Digital output level [V]
0.38
0.36
0.34
0.32
0.30 -25
0
25 Ambient temperature [C]
50
75
- 10 -
CXA1866Q
SNR vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz) 38 36 34
SNR [dB]
32 30 28 26 24 22 1 10 Input frequency [MHz] 100
Effective bit number vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz) 6.5 6.0
Effective bit number [bits]
5.5 5.0 4.5 4.0 3.5 1 10 Input frequency [MHz] 100
2nd, 3rd Harmonic distortion vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz) -20 2nd Harmonic distortion [dB] 3rd Harmonic distortion [dB] -30
2nd, 3rdHarmonic distortion [dB]
-40
-50
-60
-70 1 10 Input frequency [MHz] 100
- 11 -
CXA1866Q
Notes on Operation The CXA1866Q is a high speed A/D converter with ECL level logic input and demultiplexed TTL level output. Take notice of the followings to ensure optimum performance from this IC. <> * Grounding has a profound influence on converter performance. The higher the frequency is, the more important the way of grounding becomes. * The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using the multi-layer board. * To prevent interference between the AGND and DGND patterns and between the AVEE and DVEE lines, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVEE and DVEE lines at one point each via a ferrite-bead filter. Shorting analog and digital ground patterns in one place immediately under the A/D converter improves A/D converter performance. * Ground the power supply pins (AVEE, DVEE, DVcc) as close to each pin as possible with a 0.1F or larger ceramic chip capacitor. (Connect the AVEE pin to the AGND pattern, DVEE to DGND, and DVcc to DGND.) <> * Make the connection between the VIN pin and the analog input source as short as possible. * There is a slight offset voltage at reference voltage pins VRT and VRB. If it presents no problem in the application, the voltage can be applied directly. However, if the reference voltage is to be set precisely, apply it via a feedback circuit created using the VRTS and VRBS pins. * Make adequate by-pass for high frequency noise at VRT and VRB. The VRT pin is normally connected to AGND on the board. Bypass the VRB pin to the AGND pattern with a 0.1F or larger ceramic chip capacitor as short as possible. The 10F tantalum capacitor connected to VRB in the Application Circuit is to stop oscillation in the reference voltage generation circuit. <> * Noise at the INV pin may cause misoperation of which the cause is extremely hard to identify. If it is OK for the set voltage level to be low only, leave the pin open. If a high level voltage have to be input, bypass the INV pin to DGND with an about 0.1F ceramic chip capacitor as short as possible. It is recommend that high level input voltage is about -0.5V to -1.0V, and low level input voltage is about -1.6V to -2.5V. When inputting a high level voltage, avoid connecting directly to DGND. * The CXA1866Q has input pins for two clocks: CCLK and DCLK. For CCLK, which is used for the internal comparator, input an ECL level clock with up to the maximum conversion frequency. For DCLK, which is used for the multiplex output, input an ECL level clock with a rate half that of CCLK. Take notice of the timing between CCLK and DCLK. * It is recommended that differential signals be input to the clock input pins CCLK, NCCLK, DCLK and NDCLK. The A/D converter can be driven only by the clock input pins CCLK and DCLK, but there is a risk of unstable characteristics at maximum speeds. * If the NCCLK and NDCLK pins are not used, bypass these pins to DGND with an about 0.1F capacitor. In this time, about -1.3V voltage is generated at the NCCLK and NDCLK pins. However, this is too weak to be used as threshold voltage VBB; it can not directly drive even one ECL input load. * The clock duty cycle is designed for use at 50%. Any diversion from this percentage will have a slight effect on the maximum performance of the A/D converter, but there is no great need for adjustment. <> * P1D0 (LSB) to P1D5 (MSB), and P2D0 (LSB) to P2D5 (MSB) are demultiplex digital outputs (2 systems), and are output using the DCLK timing. The polarity of the output data can be inverted using the INV signal. - 12 -
CXA1866Q
Application circuit
DGND 48 47 46 45 44 43 42 41 40 39 38 37
DGND1
DGND2
DGND2
DGND1
DVCC2
DVCC2
DVEE
DGND3
1 DGND3 (TTL) P2D0 (TTL) P2D1 (TTL) P2D2 (TTL) P2D3 (TTL) P2D4 (TTL) P2D5 2 P2D0 3 P2D1 4 P2D2 5 P2D3 6 P2D4 7 P2D5 8 DGND3 9 DVCC2 10 11 DCLK 12 NDCLK CXA1866Q
DVCC1
DVCC1
DVCC2
DGND3 36 P1D5 35 P1D4 34 P1D3 33 P1D2 32 P1D1 31 P1D0 30 DGND3 29 DVCC2 28 INV 27 CCLK 26 NCCLK 25 INV (ECL level) P1D5 (TTL) P1D4 (TTL) P1D3 (TTL) P1D2 (TTL) P1D1 (TTL) P1D0 (TTL)
AGND
AGND
DVEE
AVEE
VRT
VRTS
VIN
AVEE
VRBS
VRB
One point shorting
13 14 15 16 17 18 19 20 21 22 23 24
AGND -5.2V +5.0V
10F
Tantalum capacitor
VRTS VRB -5.2V
Q D CP
1/2 CLK
Q
ECL buffer Analog Input CLK (ECL level)
Capacitors, if not specified, are 0.1F ceramic chip capacitors.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 13 -
CXA1866Q
CXA1866Q-PCB (6bit, 140MSPS, ADC Evaluation Board) Description The CXA1866Q PCB is a tool for customers to evaluate the performance of the CXA1866Q (6bit, 140MHz, TTL demultiplexed output, high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this tool equips. The input voltage offset generator, clock decimator, output data latches, 10-bit high-speed DAC x 2, and 26pin cable connector for 2-system digital output. This evaluation board provides full performance of the CXA1826Q and it is designed to facilitate evaluation. Features * Resolution: 6bits * Maximum conversion rate: 140MHz * Supply voltage: +5.0V, -5.2V * Conversion for clock input level: Sine wave converted to ECL level signal * Reference voltage adjustment circuit for the A/D converter * Built-in clock frequency decimation circuit: (1/2) Supply Current Item VEE (-5.2V) Vcc (+5.0V) Min. Typ. 2.0 0.6 Max. 2.2 0.7 Unit A A
Analog Input Item Input voltage (AMP. IN) (DIR. IN) Input impedance Min. -0.5 -2.0 50 Typ. Max. +0.5 0 Unit V V
Clock Input Item Input voltage (Peak to Peak) Input impedance Min. 0.6 Typ. 1.0 50 Max. Unit Vp-p
Digital Output TTL level, demultiplexed output Clock Output TTL level, Single output
- 14 -
Block Diagram
HL D/A Fullscale TTL to ECL Converter 4 6
VRB SW1 4 TTL Data Latch 2 INV CLK 2 6 ECL Data Latch CLK 2 ECL Data Latch INV CLK 2 TTL Data Latch 4 TTL to ECL Converter CLK 2 4 6 CLK TTL to ECL Converter Vref D/A Converter 2 (P1D0 to D5) INV CLK (P2D0 to D5) Vref D/A Converter 1 (P2D0 to D5)
(A/D Fullscale Adjust)
VIN Offset
D/A OUT2
VRB CXA1866Q (P1D0 to D5)
AMP.IN
A J1
CLC404
B DCLK
D/A OUT1
CCLK
DIR.IN
- 15 -
B2 B2 TTL Data Latch 6 CLK 6 TTL Data Latch 6 Q D-Latch with MR 1/2 Q CLK ECL to TTL Converter B2
B1
SW2
B1
CLK
H
L
B1
CP
(P2D0 to D5) (P1D0 to D5) DIGITAL OUT connector CLK
D
B1
: ECL Buffer, delay = 1ns
B2
: ECL Buffer, delay = 2ns
CXA1866Q
-5.2V
GND
+5.0V
CXA1866Q
Timing Chart
N-1 Analog input N N+1 N+3 N+2 N+4 N+5
PCB CLK input
TPW1 = 3.5ns A/D CCLK TPW1 = 7.0ns A/D DCLK td = 2 to 8ns A/D output (P1 side) N-4
TPW0 = 3.5ns
TPW0 = 7.0ns
N-2
N
N+2
N+4
A/D output (P2 side)
N-3
N-1
N+1
N+3
N+5
TTL CLK (CCLK/2) td = 3 to 9ns TTL Latch output (P1 side) N-6 N-4 N-2 N N+2
Delay = 4.5 to 10.5ns TTL to ECL output (P1 side) N-6 N-4 N-2 N N+2
ECL CLK (CCLK/2)
ECL Latch output (P1 side) th = 4ns D/A CLK
N-8 ts = 10ns
N-6
N-4
N-2
N
N+2
Digital CLK output td = 3 to 9ns Digital output (P1 side) N-6 N-4 N-2 N N+2
Digital output (P2 side)
N-5
N-3
N-1
N+1
N+3
- 16 -
CXA1866Q
Adjustment Methods and Notes on Operation 1) VIN Offset (VR1) The volume to adjust the AMP. IN input signal range (0V center assumed) with the A/D converter input range. 2) A/D Full Scale (VR2) The volume to adjust A/D converter VRB voltage (-2V typ.). 3) D/A Full Scale (VR3) The volume to adjust D/A converter reference voltage (-1V typ.). 4) Input pins DIR. IN ................Used to directly input to A/D converter from signal generator. AMP. IN...............Used to input to A/D converter after amplifying the signal generator input to that of -2 times by operational amplifier. CLK .....................Clock input for A/D converter and peripheral ICs. Input a sine wave of 1Vp-p. 5) Output pins D/A OUT1 ...........Analog output of D/A converter for (P1D0 to D5) data from A/D converter. D/A OUT2 ...........Analog output of D/A converter for (P2D0 to D5) data from A/D converter. DIGITAL OUT .....Output of TTL CLK (1/4 decimation) and digital data (P1D0 to D5, P2D0 to D5). 6) J1 short bar is provided to use analog input pins AMP. IN and DIR. IN. Analog input method AMP. IN input DIR. IN input with DC coupled DIR. IN input with AC coupled A SHORT OPEN 1k B OPEN SHORT 0.1F Offset Adjust with VR1. Input a offset signal. Adjust with VR1.
7) SW1 (A/D INV), SW2 (D/A INV) SW1: Output inversion (INV) switch of the CXA1866Q A/D converter SW2: Output inversion (INV) switch of the CX20201 D/A converter 8) Waveform probe pins P5, P6, P7, P9 and P11 through P38 are devised to facilitate GND connection in order to reduce the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300 mils, and there is 1.2mm throughhole at each. The signal and GND locations are suit for a Tektronix GND tip (part number 013-1185-00).
1.2mm
GND 300mil
Probe point
- 17 -
CXA1866Q
Digital Out Connector Pin Assignment Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Assignment P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 CLK Pin No. B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Assignment GND GND GND GND GND GND GND GND GND GND GND GND GND
- 18 -
CXA1866Q
Part list RESISTOR: R5, R6, R17, R18 R3, 4, 15, 20, 21, 22, 24, 27 R30, 33, 39, 41, 43, 45, 47 R49, 51, 53, 55, 57, 59, 61 R63, R78 to R91 R1, 2, 14, 19, 23, 25, 26, 28 R29, 32, 38, 40, 42, 44, 46 R48, 50, 52, 54, 56, 58, 60 R62, R64 to R77 R10, R12 R34 to R37, R93 R31, R94 R8 R16 R13, R92 R11 R7 R9 VARIABLE RESISTOR: VR1, 2, 3 CAPACITOR: C1 C5, C65, C67 C11, C12, C15 C68, C69 OTHER TRANSISTOR: Q1 IC: IC2 IC3 IC4 IC5 IC6 to 9 IC10, 11, 12 IC13, 14 IC15, 16 IC17, IC20 IC18 IC19 DIODE: D1 to D6 FERRITE BEAD: L1, L2, L3 2k (RJ-5W202) SWITCH: SW1, SW2 0.1F (CERAMIC) 3.3F (TANTALUM) 1F (TANTALUM) 33F (TANTALUM) 0.1F (CHIP CAPACITOR) AT1D-2M3-10
51 82 82 82 82 130 130 130 130 240 270 330 510 560 1k 1.3k 11k 22k
2SA970
10H116 10H131 10116 10H125 74AS574 10H124 10H176 CX20201A TL431CLP CLC404AJP TL4558P
1S2076A
ZBF253D-00
OTHERS: BNC CONNECTOR BNC-R-PC DIGITAL OUT CONNECTOR HIF3FB-26PA-2.54DS JUMPER LINE JX-1
- 19 -
CXA1866Q
Part Layout
- 20 -
Ptinted Pattern (Component plane)
- 21 -
CXA1866Q
Ptinted Pattern (Solder plane)
- 22 -
CXA1866Q
PCB Circuit Diagram
+5V (D) DGND -5.2V (D) DGND
8 7 5 3 2 6 4 1
DGND R47 82 CS Ain Aout Bout R55 82 R63 82
C48 0.1
IC9: 74AS574 BoutN
1
ContVCC 20 C41 0.1 IC12: 10H124 VCC Cin Din CoutN Dout Cout GND -5.2V (D)
1
VEE
Bin
C54 0.1 IC16: CX20201A MSB AGND2 28 D2 VREF 27 AVEE 26 NC 25 NC 24 NC 23 NC 22 NC 21 D/A OUT2 DGND
9
DoutN AoutN
DGND
2
D0 R46 130 P2D5
P38 2 P37 3 4
Q0 19 R54 130 R77 130 R76 130 D3 D4 D5 D6 D7 D8 D9 LSB
10 11 2 1
P2D5
P16 3 9 10 15 1 3
R62 130 R91 82 R90 82 R89 82 R88 82
5 6 7 8
VR3 2k D/A Full Scale C61 0.1 R92 1k IC17 TL431CP
R93 270
C66 C67 0.1 3.3
D1 Q1 18
1 2
11 1 4 1 6
P2D4
P15 4
D2 Q2 17 DGND C47 0.1 C50 0.1 P2D3
P36 P35 P34 P33
DGND
P14 5
-5.2V (D) P2D3 D3 DGND
6
+5V (D) DGND P2D4 R75 130 R74 130 R73 130 R72 130 C57 0.1 -5.2V (D) R39 82 R61 82 DGND R45 82 R53 82 R86 82 R87 82
AGND
P7 DCLK
P9 NDCLK
Q3 16 Q4 15 -5.2V (D) P2D2 P2D1 P2D0 CLK D3 D4 D5 Q3 Q4 Q5 VCC2
8 7 5 6 4 3 2 1
D4 D2 D1 D0 VEE Q2 Q1 Q0 D5 D6 Q6 13 R37 270 +5V (D)
9 10 12 13 14 16 15 11
DGND
C20 0.1 P2D2
P13 P12 7
P2D1 Q5 14 IC14: 10H176 C42 0.1 DGND R36 270
P23
-5.2V (A)
R21 82
8
R22 82 VCC1 P2D0
P11
R25 130
R28 130
DVCC2
NDCLK
DCLK
NC
DGND3
P2D5
P2D4
P2D3
P2D2
P2D1
P2D0
DGND3
L1 FERRITE BEAD
9
D7 GND CLK 11
Q7 12
+5V (A) AGND
6 5 3 2 1 4 10
12
11
10
9
8
7
VRBS P1 DGND TTL CLK1 -5V (D) DGND -5.2V (D)
8 5 4 3 6 5 3 4 2 1
C9 0.1
OUT 20 NC 19
IC20 TL431CP C46 0.1
7 6
C24 0.1
VR2 2k Full Scale DGND CS DVCC VEE Bin Ain BoutN
48
8 P2D4 P2D3 P2D2 P2D1 P2D0 DGND3 C28 0.1 P10 DVCC2 IC11: 10H124
P32 P31
IC19-2 TL4558 C53 0.1 -5.2V (D) ECL CLKN R71 130 R70 130 C56 0.1 -5.2V (D) -5.2V (D) DGND ECL CLK C52 0.1 DGND C45 0.1 R42 130 R50 130 R58 130
12
11
10
9
8
NC
12
AGND1 18 AGND NC DGND 17 C60 0.1
AGND
7
NDCLK
DVCC2
DGND3
AGND VCC Cin Din Dout Cout GND DVCC1 47
47
R10 240 C33 0.1 CoutN DVCC1 +5V DGND (D)
9 10 11 12 14 16 15 13
R11 1.3k
C6 0.1
NC
13
13
NC
DVCC2 48
Aout
Bout
4 R38 130
DCLK
P2D5
VR1 2k Off Set
R8 510
6 5
Q1 2SA970
NC
7
DGND R85 82 R84 82
13 14
CLKN CLK
INV 16 DVEE 15
DGND
C16 0.1
R9 22k DGND1 46
46
-5.2V AGND (A) C32 0.1 IC8: 74AS574
1 45
AGND -5.2V (A) DGND1 DGND2 ContVCC 20 C40 0.1 Q0 19 Q1 18 C49 0.1 DGND -5.2V (D)
5 8 7 5 3 6 4 2 1
DoutN AoutN
R7 11k
14
14
AVEE
AVEE
R44 130 R43 82
R52 130 R51 82
R60 130 R59 82
15
15
VRBS DGND2 45 DVEE 44
44
C64 0.1 -5.2V (D) DGND DGND
8
IC19-1 TL4558 C31 0.1
43
2 3 DVEE
2
1 DGND D0 D1 D2 Q2 17 Q3 16 D2 D1 D0 VEE Q2 Q1 Q0 Q4 15 IC13: 10H176
7
R13 1k +5V (D) DGND
+5.2V (A) AGND AGND
C15 VRBS 1
C18 0.1
16
16
VRB
C11 1 DVCC2 43 DVCC2
3
C13 0.1 P1D5 P22 P1D4 P21 DGND3
41 4
VRB
4 C4 0.1
C5 3.3
VIN
17
17
AGND
P2
AGND
AGND AMP.IN DGND3 42
42
AGNDAGND
18
AGND
18
NC
7 C30 0.1 P1D3 P20 DVEE D3 D4 D5 CLK D3 D4 D5 Q3 D6 Q6 13 DGND -5.2V (D)
8 4 7 5 3 2 1 6 9 10 11 12
NC
IC1: CXA1866Q
20
20
AGND DGND2 40
40
DVEE 41 P1D2 P19 DGND2
6 39
AGND C27 0.1 P1D1 P18 DGND1 DVCC1 DVCC1 DVCC2 37
37 8 38 38
DGND
R6 51
R12 240
2 3
J1 A B
19
19
VIN
VIN
P1D5
P30
IC15: CX20201A VCC1
1
AGND DGND1 39 Q5 14 C44 0.1 P1D0 P17 C29 0.1
21
21
VRTS
VRT
VRT
R17 R16 51 6 560 IC18 4 CLC404AJP R18 AGND 51 C10 C12 1 0.1 -5.2V AGND (A) AGND AGND Q4 Q5 VCC2
P4
22
C17 0.1
MSB AGND2 28 R69 130 P1D4 P29 R68 130 R83 82 R82 82
2 14 16
C62 C65 0.1 3.3
22
VRTS
DIR.IN
VRTS
D2
13 15 3
VREF 27 AGND D3 P1D3 P28 P1D2 P27 P1D1 P26 R67 130 R66 130 R65 130 R81 82 R80 82 R79 82
4
P3
AVEE P1D1 P1D2 P1D3 P1D4 P1D5 DGND3 DVCC2
9
AVEE D7 CS VEE Bin Ain GND IC10: 10H124 VCC Cin Din CoutN Dout Cout GND +5V (D) DGND IC7: 74AS574
9 10 11 14 15 12 13 16 31 32 35 1 33 36 34
23
23
AVEE
AVEE 26 D4
5
24
24
NC Q7 12 CLK 11 BoutN Aout Bout
DVCC2
AGND
31 32 35 36 33 34 10
NCCLK
CCLK
INV
DGND3
P1D0
NC
NC 25 D5 NC 24
C59 0.1 -5.2V (A)
25
26
27
28
29
30
DGND
DoutN AoutN
C23 0.1 DGND +5V (D) ContVCC 20 DGND C39 0.1 C43 0.1 Q0 19 Q1 18 Q2 17 Q3 16 D0 D1 D2 D3 D4 Q4 15 Q5 14 Q6 13 Q7 12 DGND
10
R41 82
R49 82
R57 82
6
D6 DGND C51 0.1 -5.2V (D) R40 130 R48 130 R56 130 -5.2V (D) P1D0 P25 R64 130 C55 0.1 DGND R78 82
7 8
NC 23 D7 D8
9
NC 22 NC 21 D/A OUT1 D9
10 11
25
26
27
28
29
30
INV
+5V (D) DGND
P1D0
P1D1
P1D2
P1D3
P1D4
CCLK
P1D5
DGND3
DGND3
L2 FERRITE BEAD
2 3
NCCLK
DVCC2
DGND
OUT 20 LSB NC
12
NC 19 AGND1 18 AGND NC DGND
13 14
INV
NORM
DGND
CLK A13 P1D5 A12 P1D4 A11 P1D3 A10 P1D2 A9 P1D1 A8 P1D0 A7 P2D5 A6 P2D4 A5 P2D3 A4 P2D2 A3 P2D1 A2 P2D0 A1
DGND B13 DGND B12 DGND B11 DGND B10 DGND B9 DGND B8 DGND B7 DGND B6 DGND B5 DGND B4 DGND B3 DGND B2 DGND B1
- 23 -
-5.2V (D)
4 5 6 7
-5.2V (A)
P5
P6
P8
AGND DGND 17 CLKN CLK INV 16 DVEE 15 C63 0.1 -5.2V DGND (D) L C58 0.1 DGND NORM SW2 D/A INV INV
NCCLK CCLK INV
SW1
R24 DGND 82 D5 D6 D7 R35 270 GND CLK 11 R34 270 C37 0.1 -5.2V DGND (D) DGND TTL CLK2
P24
R27 82
H
D4 DGND D5 D6
H
D1 DGND
D2
8 9
R23 130
R26 130
L
D3
R94 330 -5.2V (D)
C19 0.1
R31 330 DGND
DGND -5.2V (D)
-5.2V (D)
-5.2V DGND (D) DGND +5V (D) IC4: 10116 C25 0.1 IC6: 74AS574
1 10 9
-5.2V (D) C26 0.1 VCC ContVCC 20 D0 Q0 19 Q1 18 Q2 17 Q3 16 D3 D4
6 15 16 7
DGND IC5: 10H125 C36 0.1 VEE 8 Bin 7 DGND
2 3 12 4 13 5 14
+5V (D)
-5.2V DGND (D)
IC2: 10H116
9
C7 0.1 Bin Bin
10 11
IC3: 10H131 VEE 8 Bout 7 Bout 6
6
C21 0.1
9
Bin CinN Cin D1 D2 Cout Dout DinN Din GND VBB 1 C35 0.1 AinN 2 D5
8 9
VEE 8
9
CC
VEE 8
+5V DGND (D) C38 0.1
P24 +5V
CLK
R5 51
10 11
Bin VBB Cin
12
Bout 7 BinN Bout 5
10
D2
D1 7
(A) +5V (A) L3 +5V (D)
P28
C1 0.1
11
VBB Ain 5 Ain 4
13 14
Bout 6
11
CE2N CE1N 6
DGND Cin Cout Cout
15 16
C3 0.1
FERRITE BEAD
P29
+5V (VCC) +5V (D) AGND AGND AGND C69 33 GND
12
Cin R30 82 Aout 4 Ain 3 Aout 3 Aout 2 VCC1 1
Ain 5
R19 130
R20 82
12
S2
S1 5
13
Cin
Ain 4
13
R2
R1 4
R29 130
R1 130
R2 130
R3 82
R4 82
14
Cout
Aout 3
C14 0.1
14
Q2N
Q1N 3
15
Cout VCC2
Aout 2
DGND
C22 0.1
Q4 15 Q5 14 D6 D7
10
P25
DGND DGND DGND Q6 13 -5.2V (A) Q7 12 GND CLK 11 -5.2V (D)
P27
C2 0.1
-5.2V (D)
15
Q2
Q1 2
-5.2V (D)
DGND
-5.2V (D)
DGND
16
VCC2
VCC1 1
16
VCC2
VCC1 1
R14 130 DGND DGND DGND
R15 82
-5.2V (A)
P26
C68 33
DGND
C8 0.1 R32 130 C34 0.1 -5.2V (D) DGND R33 82
DGND
-5.2V (D)
-5.2V (VEE)
-5.2V (D)
DGND
DGND
CONNECTOR (Top View)
DIGITAL OUT DGND
CXA1866Q
CXA1866Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05
36
25
0.15
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.12 M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 24 -
0.9 0.2
13.5

▲Up To Search▲

Price & Availability of CXA1866Q

	To Download CXA1866Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .